PURPOSE: To increase the number of gates capable of being loaded on chips in the same size without augmenting skews and decreasing working speed by using an SPL circuit as a gate having a large load and an NTL circuit as a gate having a small load.
CONSTITUTION: Striplike cell regions 4a and channel regions 4b are formed alternately. Signal conductors connecting each gate are disposed in the channel regions 4b. Macro cells 5 in which two SPL gate cells 5a and two NTL gate cells 5b are combined are arranged in a lateral line in the cell region 4a. When desired logic is constituted in gate arrays composed of SPL gates and NTL gates, the SPL gates and NTL gates are used properly in response to the magnitude of load. That is, the NTL gates are employed as gates having small load capacitance CL, and the SPL gates are employed as gates having large load capacitance CL. Accordingly, when the NTL gates have small load capacitance, working speed thereof is increased fast enough not to cause any skew.